The amount of loading on a bus in a data processing system is important to the performance of the data processing system. Most data processing systems have a maximum bus loading (i.e. a maximum resistive and capacitive loading) which each bus can drive and still meet the required voltage and timing specifications for that bus. In addition, even if the loading on a bus is below the maximum specified value, the more loading on a bus, the slower the bus will operate. If multiple busses are used in a data processing system (e.g. a separate address bus and a separate data bus), it is desirable to not have a much greater load on one bus than on the other busses.
A data processor, such as a microcomputer integrated circuit, is used with a wide range of peripheral devices, for example memory integrated circuits and application specific integrated circuits (ASICs) in a data processing system. Some peripheral devices use multiplexed address and data busses, and some peripheral devices use non-multiplexed address and data busses. In addition, some peripherals may act only as bus slaves, while other peripherals may act as either bus slaves or bus masters.
It is not uncommon for a data processing system to have unequally loaded busses (e.g. address and data busses) because of the particular configuration of peripheral devices which are coupled to the data processor. A solution was needed which would more evenly distribute bus loading between various busses in a data processing system, without adding significant cost to the system.